In dynamic random access memory (DRAM) fabrication technology, continuous efforts are being undertaken to manufacture a capacitor having larger capacitance in a smaller area. Generally, a DRAM cell includes a capacitor and a transistor, the capacitor utilized for storing electric charge, and the transistor used for accessing the charge stored in the capacitor. Either the source or drain of the transistor is connected to one terminal of the capacitor. The other terminal of the transistor and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively.
The capacitor type that is most typically used in DRAM memory cells are planar capacitors, which are relatively simple to manufacture. With the advent of ultra large scale integrated (ULSI) DRAM devices, the sizes of memory cells has gotten smaller and smaller such that the area available for a single memory cell has become very small.
For very small memory cells, planar capacitors become very difficult to use reliably. Similarly, the size of the charge capable of being stored by the capacitor decreases. This results in the capacitor being very susceptible to alpha particle radiation. Additionally, as the capacitance decreases, the charge held by the storage capacitor must be refreshed often. Therefore, a variety of methods of forming capacitors have been proposed to overcome the aforesaid problems. For a stacked memory cell, Ogawa has proposed a memory cell with a crown shape having fins formed therein, entitled "METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A CAPACITOR IN A STACKED MEMORY CELL", U.S. Pat. No. 5,164,337. The method can provides a capacitor with larger surface area; however, it is relatively complicated to form a capacitor with fin structures.
A further prior art approaches to overcome these problems has resulted in the development of a capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) polysilicon storage node (see "A CAPACITOR-OVER-BIT-LINE CELL WITH HEMISPHERICAL-GRAIN STORAGE NODE FOR 64 Mb DRAMs", M. Sakao etc. Microelectronics Research Laboratories, NEC Corporation). The HSG-Si is deposited by low pressure chemical vapor deposition at the transition temperature from amorphous-Si to polycrystalline-Si. Conventional methods of increasing area by using HSG is insufficient. If the HSG-Si storage node is compared with a planar node, the increase of the surface area of the node is up to about two at best.